Several semiconductor wafer processes include wafer thinning steps. In some applications the wafers are thinned down to a thickness of less than 100 micrometers for the fabrication of integrated circuit (IC) devices. Thin wafers have the advantages of improved heat removal and better electrical operation of the fabricated IC devices. In one example, GaAs wafers are thinned down to 25 micrometers to fabricate power complementary metal oxide semiconductor (CMOS) devices with improved heat removal. Wafer thinning also contributes to a reduction of the device capacitance and to an increase of its impedance, both of which result in an overall size reduction of the fabricated device. In other applications, wafer thinning is used for 3D-Integration bonding and for fabricating through wafer vias.
Wafer thinning is usually performed via back-grinding and/or chemical mechanical polishing (CMP). CMP involves bringing the wafer surface into contact with a hard and flat rotating horizontal platter in the presence of liquid slurry. The slurry usually contains abrasive powders, such as diamond or silicon carbide, along with chemical etchants such as ammonia, fluoride, or combinations thereof. The abrasives cause substrate thinning, while the etchants polish the substrate surface at the submicron level. The wafer is maintained in contact with the abrasives until a certain amount of substrate has been removed in order to achieve a targeted thickness.
For wafer thicknesses of over 200 micrometers, the wafer is usually held in place with a fixture that utilizes a vacuum chuck or some other means of mechanical attachment. However, for wafer thicknesses of less than 200 micrometer and especially for wafers of less than 100 micrometers, it becomes increasingly difficult to mechanically hold the wafers and to maintain control of the planarity and integrity of the wafers during thinning. In these cases, it is actually common for wafers to develop microfractures and to break during CMP.
An alternative to mechanical holding of the wafers during thinning involves attaching a first surface of the device wafer (i.e., wafer processed into a device) onto a carrier wafer and then thinning down the exposed opposite device wafer surface. The bond between the carrier wafer and the device wafer is temporary and is removed upon completion of the thinning and any other processing steps.
Several temporary bonding techniques have been suggested including using of adhesive compounds that are thermally cured. In these adhesive based temporary bonding techniques a wet thick adhesive layer is applied onto the device wafer surface so that it covers all the structures of the device wafer surface including solder bumps, connectors, and integrated circuit (IC) devices. The wet adhesive layer has a typical thickness in the range of in the range of 25 to 150 micrometers. The wet adhesive layer is then brought into contact with the carrier wafer surface and the adhesive is then cured thereby resulting in bonding the device wafer to the carrier wafer. As was mentioned the bond is temporary and can be removed by dissolving the adhesive layer after processing by using chemicals, heat or radiation.
One of the problems with this process is that the thick adhesive layer causes high total thickness variations (TTV) in the wafer surface planarity. A primary TTV influence comes from the post-join thermal curing process. In particular, the thickness of the post-join adhesive layer directly correlates to the TTV error magnitude. Furthermore, a thick wet adhesive layer increases the risk of “squeezing-out” of the adhesive from the sides during the wafer joining step in the uncured state. Accordingly, it is desirable to reduce the thickness of the adhesive layer that is used for temporary bonding of thinned wafers.